1. Technical Field
Embodiments of the present disclosure relate to a semiconductor device including a plurality of memory controllers. Particularly, embodiments of the present disclosure relate to a semiconductor device including a global buffer which can be dynamically allocated to a plurality of memory controllers.
2. Related Art
A Hybrid Memory Cube (HMC) technology, including a plurality of memory cell dies and a logic die for controlling the plurality of memory cell dies, has been developed.
FIG. 1 illustrates an HMC device. The HMC includes a plurality of memory cell dies 10 and a logic die 20.
Each of the memory cell dies 10 is divided into a plurality of cell partitions 11, and the logic die 20 is divided into a plurality of logic partitions 21. Each of the cell partitions 11 may include a plurality of banks.
When the memory cell dies 10 and the logic die 20 are vertically stacked, cell partitions 11 of the memory cell dies 10 and a logic partition 21 of the logic die 20, each disposed at corresponding locations, may exchange signals through a through-silicon via (TSV) that penetrates the memory cell dies 10 and the logic die 20.
A set of the cell partitions 11 and the logic partition 21 disposed at the corresponding location is called a vault 31. The logic partition 21 operates as a memory controller that controls the cell partitions 11 in the same set, and will be referred to as a memory controller or a vault controller hereinafter.
The HMC may include a plurality of vaults 31, and each of the vaults 31 may independently operate.
In a conventional HMC device, a vault controller includes resources such as a write buffer and a prefetch buffer in order to control memory cells in a vault, but these resources are not shared by another vault controller.
Therefore, for a specific memory vault, performances of operations such as a read operation, a write operation and the like may be deteriorated when a vault controller corresponding to the specific vault includes insufficient resources.